stoper Project Status (12/16/2011 - 23:54:37)
Project File:	stoper.ise	Current State:	Programming File Generated
Module Name:	stoper	Errors:	No Errors
Target Device:	xc3s500e-4fg320	Warnings:	1 Warning
Product Version:	ISE 10.1 - WebPACK	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Timing Report)

 

stoper Partition Summary				[-]
No partition information was found.

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	124	9,312	1%
Number of 4 input LUTs	163	9,312	1%
Logic Distribution
Number of occupied Slices	124	4,656	2%
Number of Slices containing only related logic	124	124	100%
Number of Slices containing unrelated logic	0	124	0%
Total Number of 4 input LUTs	228	9,312	2%
Number used as logic	163
Number used as a route-thru	65
Number of bonded IOBs	15	232	6%
Number of BUFGMUXs	2	24	8%

 

Performance Summary				[-]
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Pt 16. gru 23:53:53 2011	0	0	10 Infos
Translation Report	Current	Pt 16. gru 23:53:59 2011	0	0	0
Map Report	Current	Pt 16. gru 23:54:05 2011	0	0	2 Infos
Place and Route Report	Current	Pt 16. gru 23:54:23 2011	0	1 Warning	2 Infos
Static Timing Report	Current	Pt 16. gru 23:54:28 2011	0	0	3 Infos
Bitgen Report	Current	Pt 16. gru 23:54:37 2011	0	0	0

Date Generated: 12/16/2011 - 23:54:37